In the electronics industry, a continuing objective is to further and further reduce the size of electronic devices while simultaneously increasing performance and speed. Cellular telephones, personal data devices, notebook computers, camcorders, and digital cameras are but a few of the consumer products that require and benefit from this ongoing miniaturization of sophisticated electronics.
Integrated circuit (“IC”) assemblies for such complex electronic systems typically have a large number of interconnected IC chips. The IC chips are usually made from a semiconductor material such as silicon or gallium arsenide. Photolithographic techniques are used to form the various semiconductor devices in multiple layers on the IC chips.
After manufacture, the IC chips are typically incorporated into packages that may contain one or several such chips. The semiconductor device chip is mounted on the surface of a substrate, for example by means of a layer of epoxy. Gold bond wires can connect electrical contact points on the upper surface of the device to the substrate. Contact balls can also be provided on the lower surface of the device for additional connections between the device and the substrate. A molding compound is used to encapsulate the die and the bond wires, providing environmental protection for the die and defining the semiconductor chip package. These chip packages or modules are then typically mounted on printed circuit wiring boards.
In conventional multi-chip modules, a number of semiconductor devices are mounted in close proximity within a single package. This eliminates separate packages for each of the semiconductor devices, improves electrical performance, and reduces the overall board space occupied by the devices.
Due to the increase in the packing density, however, the power density (the heat output concentration) of such a multi-chip module is typically higher than when the chips are separately packaged. This requires more elaborate designs for thermal management to keep the device temperatures within acceptable ranges.
In conventional multi-chip modules, the devices are connected to a substrate, and electrical connections among the devices are accomplished within the substrate. One of the technologies used to connect the devices to the substrate is called “flip chip” or face down bonding, and employs the well-known controlled collapse chip connection (or “C4”) bonding technology. With this technology, solder bumps are first formed at the chip terminals. Subsequently, the semiconductor devices are flipped over onto the substrate and the solder bumps are melted to connect to corresponding terminal pads on the substrate.
Heat management through such a structure can be critical. The internal thermal resistance and thermal performance of the flip chip interconnect technology are determined by a series of heat flow paths. By making high heat conductivity connections between the bottom of the die and the substrate, heat generated in the die can be transferred efficiently from the die to the substrate.
For applications where additional heat must be removed from the semiconductor die, the molding compound that encapsulates the die can be partially omitted from the upper surface of the die to partially expose this surface. The exposed die surface can then be put in direct physical contact with a heat spreader that overlies the semiconductor die. To enhance the cooling performance, a layer of thermal grease or the like can be spread between the die surface and the heat spreader to improve heat transfer to the heat spreader.
The heat spreader is typically formed so that it can also be attached to the underlying substrate, resulting in a mechanically strong package. Where necessary, the heat spreader can also be encapsulated in a molding compound that is formed overlying the upper surface of the package.
The heat thus flows first from the semiconductor device to the body of the semiconductor module or package into which it has been incorporated, and then to the package surface and to the heat spreader that is attached to the package surface. Unfortunately, there are drawbacks associated with the use of known heat spreaders for flip chip and other semiconductor packages. Among these drawbacks are heat spreader manufacturing costs, complicated assembly processes, and concerns about package reliability. These drawbacks can be understood, for example, by considering common prior art two-piece and single-piece structures.
One such heat spreader structure is a two-piece configuration having a stiffener with a hollow core that surrounds the flip chip, and a metal lid cover that is on top of the stiffener and the flip chip. Often, the stiffener is thicker than the metal lid. Two different metal forming processes are then required to fabricate the two different pieces of the heat spreader from two different raw metal sheets of two different thicknesses. Furthermore, assembly of a two-piece heat spreader is expensive and complicated since two layers of adhesive must be separately and carefully applied: one between the substrate and the stiffener, and a second between the stiffener and the metal lid.
In another prior art heat spreader structure, a hollow cavity and a lid are formed as a single piece. To form the cavity therein for the chip, a rather thick metal sheet needs to be used, and a substantial amount of material then needs to be removed to form the chip cavity. Thus, costly metal forming processes, like milling or casting, have to be employed to fabricate this type of heat spreader.
Consequently, there still remains a need for improved, more economical, more efficient, and more readily manufactured and assembled heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.